143 search results - page 21 / 29 » Optimality, fairness, and robustness in speed scaling design... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Increasing power densities and the high cost of low thermal resistance packages and cooling solutions make it impractical to design processors for worst-case temperature scenarios...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
ISCA
2003
IEEE
14 years 25 days ago
2003
IEEE
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...