96 search results - page 7 / 20 » Optimization of Combinational Logic Circuits Based on Compat... |
AHS
2006
IEEE
13 years 11 months ago
2006
IEEE
The following article describes and discusses the suitability of the particle swarm optimization (PSO) for the employment with blind adaptation of the directional characteristic o...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...