40 search results - page 5 / 8 » Optimization of Inductor Circuits via Geometric Programming |
INTEGRATION
2007
13 years 6 months ago
2007
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...
DAC
2009
ACM
14 years 1 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— We propose a joint power- and rate-control scheme to broadcast a multiplicity of video sequences over a broadcast channel. The formulation is intended to be general in scope, w...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...