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ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
14 years 1 months ago
An efficient SNR scalability coding framework hybrid open-close loop FGS coding
Abstract—This paper presents a novel high-efficient hybrid openclose loop based fine granularity scalable (HOCFGS) coding framework supporting different decoding complexity appli...
Xiangyang Ji, Debin Zhao, Wen Gao, Jizheng Xu, Fen...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 1 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
CGO
2010
IEEE
14 years 16 days ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the difï...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
13 years 11 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
Fast memory footprint estimation based on maximal dependency vector calculation
In data dominated applications, loop transformations have a huge impact on the lifetime of array data and therefore on memory footprint. Since a locally optimal loop transformatio...
Qubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsbe...