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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 2 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
TCAD
2008
110views more  TCAD 2008»
13 years 7 months ago
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...
Shankar Mahadevan, Federico Angiolini, Jens Spars&...
ASPLOS
2004
ACM
14 years 2 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
DAC
2009
ACM
14 years 9 months ago
Non-intrusive dynamic application profiling for multitasked applications
Application profiling ? the process of monitoring an application to determine the frequency of execution within specific regions ? is an essential step within the design process f...
Karthik Shankar, Roman L. Lysecky
CASES
2007
ACM
14 years 21 days ago
Stack size reduction of recursive programs
For memory constrained environments like embedded systems, optimization for program size is often as important, if not more important, as optimization for execution speed. Commonl...
Stefan Schäckeler, Weijia Shang