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ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
ARITH
2005
IEEE
13 years 9 months ago
Quasi-Pipelined Hash Circuits
Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on ...
Marco Macchetti, Luigi Dadda
GLVLSI
2008
IEEE
117views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Delay driven AIG restructuring using slack budget management
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 1 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
14 years 1 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi