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ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
CASES
2005
ACM
13 years 9 months ago
2005
ACM
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...