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ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
15 years 10 months ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith
CEC
2005
IEEE
15 years 9 months ago
A quantitative approach for validating the building-block hypothesis
The building blocks are common structures of high-quality solutions. Genetic algorithms often assume the building-block hypothesis. It is hypothesized that the high-quality solutio...
Chatchawit Aporntewan, Prabhas Chongstitvatana
CODES
2005
IEEE
15 years 9 months ago
Satisfying real-time constraints with custom instructions
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Pan Yu, Tulika Mitra
CODES
2005
IEEE
15 years 9 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
15 years 9 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...