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» Optimization techniques for high-performance digital circuit...
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DAC
2006
ACM
14 years 1 months ago
Circuits for energy harvesting sensor signal processing
duce system weight and volume, increase operating lifetime, The recent explosion in capability of embedded and portable decrease maintenance costs, and open new frontiers for inele...
Rajeevan Amirtharajah, Justin Wenck, Jamie Collier...
DAC
2010
ACM
13 years 11 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
DAC
2006
ACM
14 years 8 months ago
Systematic temperature sensor allocation and placement for microprocessors
Modern high performance processors employ advanced techniques for thermal management, which rely on accurate readings of on-die thermal sensors. As the importance of thermal effec...
Rajarshi Mukherjee, Seda Ogrenci Memik
TCAD
2008
81views more  TCAD 2008»
13 years 7 months ago
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
Stephen Plaza, Igor L. Markov, Valeria Bertacco
PATMOS
2007
Springer
14 years 1 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...