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ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
14 years 1 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
AIPS
2010
13 years 10 months ago
Action Elimination and Plan Neighborhood Graph Search: Two Algorithms for Plan Improvement
Compared to optimal planners, satisficing planners can solve much harder problems but may produce overly costly and long plans. Plan quality for satisficing planners has become in...
Hootan Nakhost, Martin Müller 0003
JEA
2006
83views more  JEA 2006»
13 years 7 months ago
Cache-Friendly implementations of transitive closure
In this paper we show cache-friendly implementations of the Floyd-Warshall algorithm for the All-Pairs ShortestPath problem. We first compare the best commercial compiler optimiza...
Michael Penner, Viktor K. Prasanna
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
14 years 4 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
TPCTC
2010
Springer
147views Hardware» more  TPCTC 2010»
13 years 2 months ago
Assessing and Optimizing Microarchitectural Performance of Event Processing Systems
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques