Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
As web engineering evolves web based applications complexity grows in higher orders of magnitude. Is not uncommon to find in today web based applications complex and time consumin...
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...