244 search results - page 10 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
ICPPW
2008
IEEE
14 years 2 months ago
2008
IEEE
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
RTCSA
2006
IEEE
14 years 1 months ago
2006
IEEE
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...
IPPS
1996
IEEE
13 years 12 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
CASES
2004
ACM
14 years 1 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...