244 search results - page 19 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
ICPP
1998
IEEE
14 years 1 days ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
ECIR
2004
Springer
13 years 9 months ago
2004
Springer
We simulate different architectures of a distributed Information Retrieval system on a very large Web collection, in order to work out the optimal setting for a particular set of r...
PROCEDIA
2011
12 years 10 months ago
2011
Two decades of microprocessor architecture driven by quantitative 90/10 optimization has delivered an extraordinary 1000-fold improvement in microprocessor performance, enabled by...
MICRO
1998
IEEE
14 years 1 days ago
1998
IEEE
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...