244 search results - page 31 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
BDA
2003
13 years 9 months ago
2003
: We consider the use of a cluster system with a shared nothing architecture for update-intensive autonomous databases. To optimize load balancing, we use optimistic database repli...
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...