244 search results - page 9 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
NPC
2005
Springer
14 years 1 months ago
2005
Springer
This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to op...
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
DAC
1994
ACM
1994
ACM
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
13 years 12 months ago
This paper presents a new method,based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expe...
COMSWARE
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— Minimizing the energy cost and improving thermal performance of power-limited datacenters, deploying large computing clusters, are the key issues towards optimizing the...