363 search results - page 27 / 73 » Optimizing Memory Accesses For Spatial Computation |
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
PODC
2009
ACM
14 years 8 months ago
2009
ACM
Transactional memories are typically speculative and rely on contention managers to cure conflicts. This paper explores a complementary approach that prevents conflicts by schedul...
HPCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Hypervisor-based fault tolerance (HBFT), a checkpoint-recovery mechanism, is an emerging approach to sustaining mission-critical applications. Based on virtualization technology, H...