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» Optimizing Memory Accesses For Spatial Computation
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ICPP
2003
IEEE
14 years 1 months ago
Procedural Level Address Offset Assignment of DSP Applications with Loops
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...
Youtao Zhang, Jun Yang 0002
ICPP
1991
IEEE
13 years 11 months ago
Emulation of a PRAM on Leveled Networks
There is an interesting class of ICNs, which includes the star graph and the n-way shuffle, for which the network diameter is sub-logarithmic in the network size. This paper prese...
Michael A. Palis, Sanguthevar Rajasekaran, David S...
IPPS
1997
IEEE
13 years 12 months ago
The Sparse Cyclic Distribution against its Dense Counterparts
Several methods have been proposed in the literature for the distribution of data on distributed memory machines, either oriented to dense or sparse structures. Many of the real a...
Gerardo Bandera, Manuel Ujaldon, María A. T...
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
14 years 8 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 2 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...