2932 search results - page 122 / 587 » Optimizing Memory System Performance for Communication in Pa... |
SIGGRAPH
2000
ACM
14 years 1 months ago
2000
ACM
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
SI3D
2010
ACM
14 years 4 months ago
2010
ACM
We propose a Parallel Banding Algorithm (PBA) on the GPU to compute the exact Euclidean Distance Transform (EDT) for a binary image in 2D and higher dimensions. Partitioning the i...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ICPPW
2002
IEEE
14 years 2 months ago
2002
IEEE
Different parallelization methods vary in their system requirements, programming styles, efficiency of exploring parallelism, and the application characteristics they can handle....
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...