Sciweavers

2932 search results - page 66 / 587
» Optimizing Memory System Performance for Communication in Pa...
Sort
View
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 2 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
IPPS
1998
IEEE
14 years 7 days ago
Performance Sensitivity of Space Sharing Processor Scheduling in Distributed-Memory Multicomputers
- Processor scheduling in distributed-memory systems has received considerable attention in recent years. Several commercial distributed-memory systems use spacesharing processor s...
Sivarama P. Dandamudi, Hai Yu
IPPS
1998
IEEE
14 years 7 days ago
Pin-Down Cache: A Virtual Memory Management Technique for Zero-Copy Communication
The overhead of copying data through the central processor by a message passing protocol limits data transfer bandwidth. If the network interface directly transfers the user'...
Hiroshi Tezuka, Francis O'Carroll, Atsushi Hori, Y...
IEEEPACT
1999
IEEE
14 years 8 days ago
Memory System Support for Image Processing
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sall...
DEXA
1994
Springer
164views Database» more  DEXA 1994»
14 years 3 days ago
PPOST: A Parallel Database in Main Memory
We present the PPOST-architecture (Persistent Parallel Object Store) for main-memory database systems on parallel computers, that is suited for applications with challenging perfor...
László Böszörményi,...