Sciweavers

2932 search results - page 88 / 587
» Optimizing Memory System Performance for Communication in Pa...
Sort
View
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
ICPP
2009
IEEE
14 years 2 months ago
Investigating High Performance RMA Interfaces for the MPI-3 Standard
—The MPI-2 Standard, released in 1997, defined an interface for one-sided communication, also known as remote memory access (RMA). It was designed with the goal that it should p...
Vinod Tipparaju, William Gropp, Hubert Ritzdorf, R...
ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
14 years 2 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
EUROPAR
2009
Springer
14 years 2 months ago
Process Mapping for MPI Collective Communications
It is an important problem to map virtual parallel processes to physical processors (or cores) in an optimized way to get scalable performance due to non-uniform communication cost...
Jin Zhang, Jidong Zhai, Wenguang Chen, Weimin Zhen...
DATE
1997
IEEE
75views Hardware» more  DATE 1997»
14 years 8 days ago
Using constraint logic programming in memory synthesis for general purpose computers
In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory ...
Renate Beckmann, Jürgen Herrmann