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ISLPED
2005
ACM
99views Hardware» more  ISLPED 2005»
15 years 10 months ago
A low-power bus design using joint repeater insertion and coding
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
Srinivasa R. Sridhara, Naresh R. Shanbhag
ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
15 years 10 months ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
WMPI
2004
ACM
15 years 10 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ECUMN
2004
Springer
15 years 10 months ago
A Hybrid Overlay Topology for Wide Area Multicast Sessions
Abstract. MPNT (Multicast Proxies NeTwork) is an overlay architecture that was first conceived to provide multicast access to unicast-only users, like TutTelNet distant students. ...
Rédouane Benaini, Karim Sbata, Pierre Vince...
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
15 years 10 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...