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ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
13 years 11 months ago
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-S...
ISQED
2007
IEEE
106views Hardware» more  ISQED 2007»
14 years 3 months ago
Passive Modeling of Interconnects by Waveform Shaping
In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models pas...
Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGau...
CLUSTER
2007
IEEE
14 years 1 months ago
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
Reza Zamani, Ahmad Afsahi, Ying Qian, V. Carl Hama...
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 10 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
ASPDAC
2005
ACM
138views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Crowdedness-balanced multilevel partitioning for uniform resource utilization
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitio...
Yongseok Cheon, Martin D. F. Wong