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ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 9 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
ANCS
2010
ACM
13 years 5 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
IISWC
2006
IEEE
14 years 1 months ago
An Architectural Characterization Study of Data Mining and Bioinformatics Workloads
— Data mining is the process of automatically finding implicit, previously unknown, and potentially useful information from large volumes of data. Recent advances in data extrac...
Berkin Özisikyilmaz, Ramanathan Narayanan, Jo...
JSA
2008
91views more  JSA 2008»
13 years 7 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
ISPAN
1996
IEEE
13 years 11 months ago
Design and evaluation of an environment APE for automatic parallelization of programs
In this paper, we have presented the design and evaluation of a compiler system, called APE,for automatic parallelization of scientific and engineering applications on distributed...
Vipin Chaudhary, Cheng-Zhong Xu, Sumit Roy, Jialin...