2703 search results - page 173 / 541 » Optimizing memory transactions |
ALGORITHMICA
2008
13 years 10 months ago
2008
In this paper we investigate the design and analysis of algorithms resilient to memory faults. We focus on algorithms that, despite the corruption of some memory values during the...
JSA
2007
13 years 10 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
ICC
2007
IEEE
14 years 4 months ago
2007
IEEE
— As the capacity of the two-dimensional coherent optical memory (2D-COM) increases, the bit error rate (BER) performance of the system is degraded due to increased twodimensiona...
IPPS
2005
IEEE
14 years 3 months ago
2005
IEEE
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...