2703 search results - page 190 / 541 » Optimizing memory transactions |
102
Voted
ISCA
1998
IEEE
15 years 6 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
153
Voted
ARITH
1993
IEEE
15 years 6 months ago
1993
IEEE
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
125
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JPDC
2007
15 years 2 months ago
2007
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
131
Voted
NPL
2002
15 years 2 months ago
2002
A neural network model of associative memory is presented which unifies the two historically more relevant enhancements to the basic Little-Hopfield discrete model: the graded resp...
118
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KES
2010
Springer
15 years 1 months ago
2010
Springer
Evolving Takagi Sugeno (eTS) models are optimised for use in applications with high sampling rates. This mode of use produces excellent prediction results very quickly and with lo...