2703 search results - page 194 / 541 » Optimizing memory transactions |
100
click to vote
IWINAC
2005
Springer
15 years 8 months ago
2005
Springer
This paper presents a method for spatial navigation performed mainly on past experiences. The past experiences are remembered in their temporal context, i.e. as episodes of events....
146
Voted
WMPI
2004
ACM
15 years 8 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
101
Voted
ISLPED
2000
ACM
15 years 7 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
DATE
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
116
click to vote
LICS
1997
IEEE
15 years 6 months ago
1997
IEEE
We consider a class of infinite two-player games on finitely coloured graphs. Our main question is: given a winning condition, what is the inherent blow-up (additional memory) of ...