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ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
14 years 28 days ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
RTS
2008
134views more  RTS 2008»
13 years 7 months ago
On earliest deadline first scheduling for temporal consistency maintenance
A real-time object is one whose state may become invalid with the passage of time. A temporal validity interval is associated with the object state, and the real-time object is te...
Ming Xiong, Qiong Wang, Krithi Ramamritham
WMPI
2004
ACM
14 years 2 months ago
Compiler-optimized usage of partitioned memories
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...
Lars Wehmeyer, Urs Helmig, Peter Marwedel
RTSS
1999
IEEE
14 years 1 months ago
Deriving Deadlines and Periods for Real-Time Update Transactions
Typically, temporal validity of real-time data is maintained by periodic update transactions. In this paper, we examine the problem of period and deadline assignment for these upda...
Ming Xiong, Krithi Ramamritham
CGO
2003
IEEE
14 years 2 months ago
Optimizing Memory Accesses For Spatial Computation
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
Mihai Budiu, Seth Copen Goldstein