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» Optimizing pipelines for power and performance
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ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
14 years 1 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 1 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
ICPR
2000
IEEE
14 years 17 days ago
Transparent Parallel Image Processing by way of a Familiar Sequential API
This paper describes an infrastructure that enables transparent development of image processing software for parallel computers. The infrastructure’s main component is an image ...
Frank J. Seinstra, Dennis Koelma
IJCAI
2007
13 years 9 months ago
Symmetric Component Caching
Caching, symmetries, and search with decomposition are powerful techniques for pruning the search space of constraint problems. In this paper we present an innovative way of effi...
Matthew Kitching, Fahiem Bacchus
PE
2010
Springer
137views Optimization» more  PE 2010»
13 years 6 months ago
Tail-robust scheduling via limited processor sharing
From a rare events perspective, scheduling disciplines that work well under light (exponential) tailed workload distributions do not perform well under heavy (power) tailed worklo...
Jayakrishnan Nair, Adam Wierman, Bert Zwart