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» Optimizing pipelines for power and performance
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 2 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ARITH
2005
IEEE
14 years 1 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 1 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
13 years 11 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
GLOBECOM
2008
IEEE
13 years 8 months ago
Network Planning for Next-Generation Metropolitan-Area Broadband Access under EPON-WiMAX Integration
Abstract--This paper tackles a fundamental problem of network planning and dimensioning under EPON-WiMAX integration for next-generation wireless metropolitan-area broadband access...
Bin Lin, Pin-Han Ho, Xuemin Shen, Frank Chih-Wei S...