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» Optimizing pipelines for power and performance
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RTCSA
2006
IEEE
14 years 2 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
14 years 1 months ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
ERSA
2006
129views Hardware» more  ERSA 2006»
13 years 9 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
TMC
2010
130views more  TMC 2010»
13 years 6 months ago
SYNAPSE++: Code Dissemination in Wireless Sensor Networks Using Fountain Codes
—This paper presents SYNAPSE++, a system for over the air reprogramming of wireless sensor networks (WSNs). In contrast to previous solutions, which implement plain negative ackn...
Michele Rossi, Nicola Bui, Giovanni Zanca, Luca St...
LCTRTS
2010
Springer
13 years 6 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...