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» Optimizing pipelines for power and performance
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ISLPED
1996
ACM
76views Hardware» more  ISLPED 1996»
13 years 12 months ago
Comparison of high speed voltage-scaled conventional and adiabatic circuits
The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Usin...
David J. Frank
INFORMATIKTAGE
2008
13 years 9 months ago
An Energy-Efficient Routing Protocol for Linear Wireless Sensor Networks
: Economical power use is essential to allow for long-lasting operation of wireless sensor networks. This applies equally to linear sensor networks as they emerge when sensors are ...
Marco Zimmerling
TVLSI
2002
97views more  TVLSI 2002»
13 years 7 months ago
Techniques for energy-efficient communication pipeline design
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
Gang Qu, Miodrag Potkonjak
ICCD
2000
IEEE
137views Hardware» more  ICCD 2000»
14 years 4 days ago
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh...
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...