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BWCCA
2010
13 years 2 months ago
Advanced Design Issues for OASIS Network-on-Chip Architecture
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, K...
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 9 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
ISITA
2010
13 years 5 months ago
Performance analysis and optimal power allocation for hybrid incremental relaying
Relaying technique has been developed considerable attention in response to improve reliability and to extend wireless network coverage. One of conventional relaying technique, inc...
Jaeyoung Lee, Sung-il Kim, Jun Heo
CODES
2003
IEEE
14 years 1 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
NETWORKING
2004
13 years 9 months ago
Power Adaptation Based Optimization for Energy Efficient Reliable Wireless Paths
We define a transmission power adaptation-based routing technique that finds optimal paths for minimum energy reliable data transfer in multi-hop wireless networks. This optimal ch...
Suman Banerjee, Archan Misra