620 search results - page 34 / 124 » Optimizing the BSD routing system for parallel processing |
TASE
2011
IEEE
13 years 3 months ago
2011
IEEE
—This paper reports the design and development processes of a totally decoupled flexure-based XYZ parallel-kinematics micropositioning stage with piezoelectric actuation. The un...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
PE
2006
Springer
13 years 8 months ago
2006
Springer
In this paper, we study the problem of dynamic allocation of the resources of a general parallel processing system, comprised of M heterogeneous processors and M heterogeneous tra...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
A parallel structure to do spectrum sensing in Cognitive Radio (CR) at sub-Nyquist rate is proposed. The structure is based on Compressed Sensing (CS) that exploits the sparsity o...