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» Optimizing the FPGA Implementation of HRT Systems
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FPL
2000
Springer
77views Hardware» more  FPL 2000»
14 years 12 days ago
Multiple-Wordlength Resource Binding
This paper describes a novel resource binding technique for use in multiple-wordlength systems implemented in FPGAs. It is demonstrated that the multiple-wordlength binding problem...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
ERSA
2008
103views Hardware» more  ERSA 2008»
13 years 10 months ago
A Hardware Accelerator for k-th Nearest Neighbor Thinning
This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning al...
Tobias Schumacher, Robert Meiche, Paul Kaufmann, E...
RSP
2008
IEEE
118views Control Systems» more  RSP 2008»
14 years 3 months ago
Functional DIF for Rapid Prototyping
Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity in...
William Plishker, Nimish Sane, Mary Kiemb, Kapil A...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 2 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 10 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...