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» Optimizing the FPGA Implementation of HRT Systems
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RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
14 years 4 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 3 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
HOTI
2008
IEEE
14 years 4 months ago
Constraint Repetition Inspection for Regular Expression on FPGA
— Recent network intrusion detection systems (NIDS) use regular expressions to represent suspicious or malicious character sequences in packet payloads in a more efficient way. ...
Miad Faezipour, Mehrdad Nourani
ISDA
2006
IEEE
14 years 4 months ago
Efficient Multiplier over Finite Field Represented in Type II Optimal Normal Basis
- Elliptic curve cryptography plays a crucial role in networking and information security area, and modular multiplication arithmetic over finite field is a necessary computation p...
Youbo Wang, Zhiguang Tian, Xinyan Bi, Zhendong Niu
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 4 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...