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APCSAC
2006
IEEE
14 years 1 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
ISCAPDCS
2007
13 years 9 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
EUROPAR
2008
Springer
13 years 9 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...
OSDI
1994
ACM
13 years 8 months ago
A Caching Model of Operating System Kernel Functionality
Operating system research has endeavored to develop micro-kernels that provide modularity, reliability and security improvements over conventional monolithic kernels. However, the...
David R. Cheriton, Kenneth J. Duda
RSP
2000
IEEE
111views Control Systems» more  RSP 2000»
13 years 12 months ago
Reconfigurable Instruction Set Processors: A Survey
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
Francisco Barat, Rudy Lauwereins