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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
13 years 12 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun
PPOPP
1997
ACM
13 years 12 months ago
Performance Implications of Communication Mechanisms in All-Software Global Address Space Systems
Global addressing of shared data simplifies parallel programming and complements message passing models commonly found in distributed memory machines. A number of programming sys...
Beng-Hong Lim, Chi-Chao Chang, Grzegorz Czajkowski...
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
14 years 8 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
PLDI
2006
ACM
14 years 1 months ago
Optimizing data permutations for SIMD devices
The widespread presence of SIMD devices in today’s microprocessors has made compiler techniques for these devices tremendously important. One of the most important and difficul...
Gang Ren, Peng Wu, David A. Padua