1990 search results - page 9 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
RTSS
2008
IEEE
14 years 1 months ago
2008
IEEE
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
MICRO
2003
IEEE
14 years 24 days ago
2003
IEEE
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...