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» Optimizing yield in global routing
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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
13 years 11 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
ICNP
2005
IEEE
14 years 1 months ago
Landmark Guided Forwarding
In this paper we focus on the problems of maintaining Ad Hoc network connectivity in the presence of node mobility whilst providing globally efficient and robust routing. The com...
Menghow Lim, Adam Chesterfield, Jon Crowcroft, Jul...
ENVSOFT
2007
258views more  ENVSOFT 2007»
13 years 7 months ago
Optimal groundwater monitoring design using an ant colony optimization paradigm
Groundwater long-term monitoring (LTM) is required to assess the performance of groundwater remediation and human being health risk at post-closure sites where groundwater contami...
Yuanhai Li, Amy B. Chan Hilton
INFOCOM
2005
IEEE
14 years 1 months ago
Fairness and optimal stochastic control for heterogeneous networks
— We consider optimal control for general networks with both wireless and wireline components and time varying channels. A dynamic strategy is developed to support all traffic w...
Michael J. Neely, Eytan Modiano, Chih-Ping Li
DAC
1997
ACM
13 years 11 months ago
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
Avaneendra Gupta, John P. Hayes