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» Optimizing yield in global routing
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ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
14 years 2 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper
OPODIS
2010
13 years 5 months ago
On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors
We consider the problem of scheduling dependent real-time tasks for overloads on a multiprocessor system, yielding best-effort timing assurance. The application/scheduling model in...
Piyush Garyali, Matthew Dellinger, Binoy Ravindran
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 1 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
ACCV
2010
Springer
13 years 2 months ago
A Convex Image Segmentation: Extending Graph Cuts and Closed-Form Matting
Abstract. Image matting and segmentation are two closely related topics that concern extracting the foreground and background of an image. While the methods based on global optimiz...
Youngjin Park, Suk I. Yoo
DAC
2009
ACM
14 years 8 months ago
Double patterning lithography friendly detailed routing with redundant via consideration
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
Kun Yuan, Katrina Lu, David Z. Pan