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» Optimum wire sizing of RLC interconnect with repeaters
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VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
14 years 3 days ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
14 years 4 months ago
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Harshit K. Shah, Pun Shiu, Brian Bell, Mamie Aldre...
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
14 years 1 months ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman
VLSID
1999
IEEE
104views VLSI» more  VLSID 1999»
14 years 3 days ago
Interconnect Optimization Strategies for High-Performance VLSI Designs
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
TVLSI
2008
78views more  TVLSI 2008»
13 years 7 months ago
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng...