Sciweavers

1560 search results - page 215 / 312
» Order Functions and Evaluation Codes
Sort
View
DATE
2010
IEEE
130views Hardware» more  DATE 2010»
15 years 8 months ago
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming C...
IPPS
1995
IEEE
15 years 8 months ago
Index translation schemes for adaptive computations on distributed memory multicomputers
Current research in parallel programming is focused on closing the gap between globally indexed algorithms and the separate address spaces of processors on distributed memory mult...
Bongki Moon, Mustafa Uysal, Joel H. Saltz
WSC
2008
15 years 7 months ago
A simulation template for modeling tunnel shaft construction
This paper presents the design and development of a template for analyzing shaft construction projects. It is suitable for integration with the existing Tunneling template of the ...
Fangyi Zhou, Simaan M. AbouRizk, Siri Fernando
ACSAC
2008
IEEE
15 years 6 months ago
Practical Applications of Bloom Filters to the NIST RDS and Hard Drive Triage
Much effort has been expended in recent years to create large sets of hash codes from known files. Distributing these sets has become more difficult as these sets grow larger. Mea...
Paul F. Farrell Jr., Simson L. Garfinkel, Douglas ...
CF
2005
ACM
15 years 6 months ago
Reducing misspeculation overhead for module-level speculative execution
Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multip...
Fredrik Warg, Per Stenström