59 search results - page 5 / 12 » Out-of-Order Commit Processors |
CF
2006
ACM
14 years 1 months ago
2006
ACM
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
HIPEAC
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...