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» Overscaling-friendly timing speculation architectures
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ICSE
2000
IEEE-ACM
13 years 11 months ago
Software architecture: a roadmap
Over the past decade software architecture has received increasing attention as an important subfield of software engineering. During that time there has been considerable progres...
David Garlan
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 24 days ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
IPPS
2010
IEEE
13 years 5 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
ICCSA
2004
Springer
14 years 27 days ago
Speculative Parallelization of a Randomized Incremental Convex Hull Algorithm
Finding the fastest algorithm to solve a problem is one of the main issues in Computational Geometry. Focusing only on worst case analysis or asymptotic computations leads to the d...
Marcelo H. Cintra, Diego R. Llanos Ferraris, Bel&e...
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 1 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri