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» Overview on Low Power SoC Design Technology
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ACE
2004
186views Education» more  ACE 2004»
15 years 5 months ago
TinkerNet: A Low-Cost Networking Laboratory
The 2002 SIGCOMM Workshop on Educational Challenges for Computer Networking [Kur02a] exposed many issues related to teaching computer networking with the need for a laboratory in ...
Michael Erlinger, Mart Molle, Titus Winters, Chris...
108
Voted
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
15 years 5 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 10 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 10 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
KES
2005
Springer
15 years 9 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee