339 search results - page 37 / 68 » Overview on Low Power SoC Design Technology |
PATMOS
2004
Springer
14 years 27 days ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
ISLPED
2003
ACM
14 years 24 days ago
2003
ACM
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are use...
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
ISVLSI
2002
IEEE
14 years 13 days ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...