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» Overview on Low Power SoC Design Technology
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GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
13 years 12 months ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
14 years 2 months ago
Dynamic thermal management in 3D multicore architectures
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
Ayse Kivilcim Coskun, José L. Ayala, David ...
MSWIM
2006
ACM
14 years 1 months ago
Performance evaluation of web services invocation over Bluetooth
Mobile devices should allow users to exploit services anytime, without any place restriction and in a transparent way. The Bluetooth technology achieves this feature, by providing...
Vincenzo Auletta, Carlo Blundo, Emiliano De Cristo...
DRM
2007
Springer
14 years 1 months ago
Digital rights management: desirable, inevitable, and almost irrelevant
provides a very brief overview of some of the main points. References are given to my papers, where those points are explained in more detail, and citations are provided to the ext...
Andrew M. Odlyzko