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» Overview on Low Power SoC Design Technology
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SENSYS
2004
ACM
14 years 27 days ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
PARELEC
2000
IEEE
13 years 11 months ago
Parallel Computing Environments and Methods
Recent advances in high-speed networks, rapid improvements in microprocessor design, and availability of highly performing clustering software implementations enables cost-effecti...
Ghassan Fadlallah, Michel Lavoie, Louis-A. Dessain...
CORR
2008
Springer
96views Education» more  CORR 2008»
13 years 7 months ago
High Efficiency 3-Phase Cmos Rectifier with Step Up and Regulated
: This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditi...
J.-C. Crebier, Y. Lembeye, H. Raisigel, O. Deleage...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 7 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
14 years 4 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...