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MICRO
2003
IEEE
142views Hardware» more  MICRO 2003»
14 years 21 days ago
Hardware Support for Control Transfers in Code Caches
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...
Ho-Seop Kim, James E. Smith
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 5 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
JNW
2007
86views more  JNW 2007»
13 years 7 months ago
Linux Software Router: Data Plane Optimization and Performance Evaluation
- Recent technological advances provide an excellent opportunity to achieve truly effective results in the field of open Internet devices, also known as Open Routers or ORs. Even t...
Raffaele Bolla, Roberto Bruschi
IISWC
2009
IEEE
14 years 2 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
CCS
2009
ACM
14 years 2 months ago
Countering kernel rootkits with lightweight hook protection
Kernel rootkits have posed serious security threats due to their stealthy manner. To hide their presence and activities, many rootkits hijack control flows by modifying control d...
Zhi Wang, Xuxian Jiang, Weidong Cui, Peng Ning