Sciweavers

223 search results - page 43 / 45
» POWER4 system microarchitecture
Sort
View
HPCA
2008
IEEE
14 years 7 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
LCTRTS
2009
Springer
14 years 2 months ago
Push-assisted migration of real-time tasks in multi-core processors
Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily incre...
Abhik Sarkar, Frank Mueller, Harini Ramaprasad, Si...
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
14 years 2 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
14 years 2 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
14 years 2 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee